The present invention relates to an integrated current-limiter device for power MOS transistors and a process for the manufacture thereof.
A current limiter for an MOS power transistor can be accomplished through the use of an MOS current-sensing transistor connected in parallel with the power transistor and in series with a sensing resistance. The voltage produced across this resistance drives the base of a bipolar control transistor so as to cause its firing (and thus the limiting of the gate voltage of the sensing and power transistors) when the voltage across the resistance (and thus the current flowing through the sensing and power transistors) exceeds a preset threshold.
A known monolithic integrated embodiment of that current limiter provides for the formation of MOS transistors of the vertical type with the drain coincident with a semiconductor substrate of a first type of conductivity with a superimposed epitaxial layer of the same type of conductivity, but less highly doped, and of a bipolar transistor of the lateral type in a surface area of the epitaxial layer. More precisely, inside the epitaxial layer there is a base region of the second type of conductivity, inside which there are highly-doped regions of emitter and collector of the first type of conductivity.
This integrated embodiment of the current limiter has the drawback that with the lateral bipolar transistor there is associated a vertical bipolar parasitic transistor with base regions and emitter coincident with those of the lateral bipolar transistor and a collector region coincident with the substrate and thus with the drains of the MOS transistors. The maximum operating voltage of the device is thus determined by the breakdown voltage of the vertical bipolar parasitic transistor, rather than by the breakdown voltage of the power MOS transistor. The object of the present invention is thus that of accomplishing an integrated current-limiter device of the type and a corresponding process for its manufacture, wherein the effects of the vertical bipolar parasitic transistor are reduced to a minimum while the conduction of the lateral bipolar transistor is fostered in the presence of a base bias.
According to one of the innovative teachings set forth herein, this object is attained through an integrated current-limiter device for MOS power transistors provided with a bipolar control transistor, comprising a semiconductor substrate of a first type of conductivity, an epitaxial layer of the same type of conductivity superimposed over the substrate and, for the bipolar control transistor, a base region of a second type of conductivity contained in the epitaxial layer and accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts, wherein the base region comprises at least one highly-doped deep-body region which contains almost completely the emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which, together with the first deep-body region, contains the emitter region, and there is at least one first portion of a layer of polysilicon on gate oxide which is superimposed over an area of the base region included between the regions of collector and emitter and is electrically connected to the collector contact.
Other innovative teachings set forth herein provide a process for the manufacture of the current-limiter device, wherein it comprises the formation of field oxide on a lightly-doped epitaxial layer of a first type of conductivity superimposed over a highly-doped substrate of the same type of conductivity, the definition and implantation of at least one highly-doped deep-body region of a second type of conductivity, the definition of active areas of the substrate deprived by selective removal of the field oxide, the growth of a layer of gate oxide, the deposition and doping of a layer of polysilicon, the definition of at least one first portion of the layer of polysilicon, the implantation of lightly-doped body regions of the second type of conductivity, the definition and implantation of an intermediate-doped region of the second type of conductivity self-aligned with the first portion of the layer of polysilicon, the diffusion of the body regions and of the intermediate-doped region, the definition, the implantation and the diffusion of highly-doped regions of collector and emitter of the first type of conductivity of which the first contained inside the body region and the second contained in the deep-body region and the intermediate-doped region, the creation of base, emitter and collector contacts for the base region and the regions of emitter and collector and the electrical connection of the first portion of the layer of polysilicon with the collector contact.
There is thus obtained a lateral bipolar control transistor for a current-limiter device for an MOS power transistor, wherein the emitter region is completely enclosed by the deep-body region and by the intermediate-doped region; it is thus possible to reduce to a minimum the gain of the associated vertical bipolar parasitic transistor. Such gain is further reduced thanks to the alignment between the intermediate-doped region and the first portion of the layer of polysilicon, whose connection to the collector contact determines the reversal of the conductivity of the body region in the proximity of the collector region and thus fosters the conduction of the lateral bipolar transistor, conduction that takes place only in the presence of a direct bias of the base-emitter junction. The reduction of the gain corresponds to the increase in the breakdown voltage of the vertical bipolar parasitic transistor, and thus me maximum voltage at which the device can operate is no longer limited by this parasitic component, but by the breakdown voltage of the power MOS transistor.